Field of the Invention
The invention relates to a controller, and more particularly to a memory controller capable of providing an individual reference voltage for each bit.
Description of the Related Art
In existing computer systems, the physical interface of Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) is a standard protocol specification defined for connecting the memory controller to the memory devices, including the DDR1, DDR2, DDR3, DDR4 and so on. This protocol defines all the signals, the relationship and the timing between the signals, and how the signal transmission goes between memory and memory controller via this interface.
Using existing technology, the memory controller first gives the address signal through the address bus pins, and then selectively provides the read/write control signal through the control pins. The address signal and the read/write control signal enter the physical layer via the physical layer interface, and the receiver in the DDR physical layer receives the data signal from the memory controller or returns the data signal read from the memory according to the read/write control signals.
When reading data from the memory device, the memory controller must sample the data signal according to the clock signal to obtain the content of the data. Therefore, how to accurately sample the data read from the memory is a key factor affecting the performance of the memory controller product.